This article is part of our High-Frequency PCB Fabrication Guide.
In high-speed PCB fabrication, differential signaling requires both controlled impedance and matched propagation delay between pairs.
Designs can meet single-ended 50-ohm targets while failing differential 100-ohm specifications. The difference is not just impedance magnitude. It is odd-mode and even-mode coupling, intra-pair skew from glass weave effects, and mode conversion from asymmetry.
This guide addresses the fabrication factors that determine differential pair performance in PCIe, Ethernet, and high-speed serial interfaces.
Differential Impedance Versus Single-Ended Impedance
A differential pair carries two signals: positive and negative. The receiver responds to the voltage difference between them.
Differential impedance is not simply twice the single-ended impedance.
Differential impedance depends on:
- • Single-ended impedance of each trace (Zo)
- • Coupling coefficient between traces (k)
- • Trace spacing relative to dielectric height
For microstrip differential pairs:
Zdiff approximately equals 2 times Zo times (1 minus k)
To achieve 100-ohm differential impedance, typical designs use 50 to 55 ohm single-ended traces with spacing that creates the correct coupling.
Odd-Mode and Even-Mode Impedance
Any signal on a differential pair can be decomposed into two modes:
Odd Mode (Differential)
Signals are equal magnitude, opposite polarity. This is the intended differential signal.
Impedance typically 45 to 55 ohms for 100-ohm differential pairs.
Even Mode (Common)
Signals are equal magnitude, same polarity. This is noise or EMI.
Impedance typically 55 to 65 ohms for the same pair.
Differential impedance equals 2 times odd-mode impedance. If odd-mode is 50 ohms, differential is 100 ohms.
Common Differential Impedance Targets by Interface
Notice that impedance tolerance tightens as data rate increases. PCIe Gen 5 allows only plus or minus 8 percent, compared to plus or minus 15 percent for Gen 3.
Trace Spacing and Coupling Effects
Differential impedance depends heavily on trace-to-trace spacing (S) relative to trace height above ground plane (H).
Typical Spacing Guidelines:
- • Tightly coupled: S/H ratio less than 1.0 (strong coupling, lower differential Z)
- • Moderately coupled: S/H ratio 1.0 to 2.0 (typical for 100-ohm pairs)
- • Loosely coupled: S/H ratio greater than 2.0 (weak coupling, higher differential Z)
Too Close (Over-Coupled):
Differential impedance drops below target. Crosstalk to adjacent pairs increases.
Too Far (Under-Coupled):
Differential impedance rises above target. Pairs behave more like independent single-ended traces.
Intra-Pair Skew and Glass Weave Effects
Even if differential impedance is correct, propagation delay mismatch between the two traces creates timing skew.
The primary source of intra-pair skew in production is glass weave effect.
Glass Weave Skew Mechanism
FR-4 consists of woven glass fabric impregnated with epoxy resin. Glass has higher dielectric constant (Dk approximately 6.0) than resin (Dk approximately 3.0).
If one trace of a differential pair runs over a glass bundle and the other runs between bundles (resin-rich region), they experience different effective Dk values.
This creates propagation delay mismatch, introducing skew.
Typical Glass Weave Skew Contribution
For PCIe Gen 5 with 8 ps total skew budget, a 6-inch trace on 7628 weave can consume 18 to 30 ps if aligned with the weave, exceeding the budget by 3x.
Mode Conversion and Common-Mode Noise
When differential pairs have asymmetry, differential signals convert to common-mode noise.
Common-mode noise radiates more efficiently than differential signals and can cause EMI failures.
Sources of Mode Conversion
Via Asymmetry:
One via offset by 5 to 10 mil from the other. Creates inductance imbalance and mode conversion.
Trace Width Mismatch:
Fabrication tolerance variation. One trace 4.5 mil, the other 5.5 mil. Creates impedance imbalance.
Reference Plane Discontinuity:
One trace over solid ground, the other over a split or cutout. Creates return path asymmetry.
Component Placement Error:
AC coupling capacitors misaligned. One capacitor closer to trace than the other.
Mode conversion is measured as Sdc21 or Scd21. Target values below -30 dB for high-speed differential interfaces.
How Fabrication Tolerances Affect Differential Impedance
Production PCBs have tolerance variation that affects differential impedance:
For PCIe Gen 5 with plus or minus 8 percent tolerance, total fabrication variation can consume the entire budget. Tight process control is required.
Differential Pair Layout Best Practices
Route pairs at 10 to 20 degrees to panel edge
Reduces glass weave skew contribution to 1 to 2 ps per inch on 2116 or 7628 weave.
Keep via transitions symmetric
Both vias on the same layer, same distance from reference plane, same anti-pad diameter.
Avoid reference plane splits under differential pairs
Keep solid ground or power reference continuous under entire length.
Validate stack-up with field solver before fabrication
Confirm differential impedance at nominal dimensions and worst-case tolerance corners.
Use TDR to measure fabricated boards
Verify actual differential impedance on first article. Compare to simulation.
Differential Pair Fabrication Validation Checklist
Differential Pairs Require Process Control
Differential impedance is not just layout geometry. It is fabrication tolerance, glass weave structure, and process repeatability.
For PCIe Gen 4 and above, validate differential impedance on first article builds before production release.