This article is part of our High-Frequency PCB Fabrication Guide.
Controlled impedance PCB fabrication is the foundation of reliable high-frequency signal transmission.
When trace impedance is tightly controlled, signal reflections decrease, insertion loss becomes predictable, and link margins remain stable across production lots.
This guide explains how impedance tolerance is achieved in manufacturing, how to validate it before production, and which design decisions directly affect first-pass success.
What Controlled Impedance Means in PCB Fabrication
Controlled impedance refers to the manufacturing process used to achieve a specific characteristic impedance within a defined tolerance range.
The goal is to match the transmission line impedance to the source and load impedances across the entire signal path.
Impedance depends on four physical parameters:
- • Trace width
- • Dielectric thickness (height above reference plane)
- • Copper thickness
- • Dielectric constant (Dk or Er)
In fabrication, each of these parameters carries tolerance. The challenge is to manage cumulative variation so final impedance remains within specification.
Tolerance Stack-Up and Impedance Variation
Each fabrication parameter contributes to final impedance variation. Understanding which parameters dominate the tolerance budget allows better design decisions.
Typical Fabrication Tolerances and Impedance Impact
For a 50-ohm target, plus or minus 10 percent tolerance (45 to 55 ohms) is standard industry practice. For high-speed designs, plus or minus 5 percent (47.5 to 52.5 ohms) is recommended.
Stack-Up Design and Impedance Calculation Workflow
Achieving controlled impedance in fabrication requires collaboration between design and manufacturing.
- Define target impedance: Specify 50, 85, 90, or 100 ohms based on interface requirements (USB, PCIe, Ethernet, etc.)
- Request fabricator stack-up: Obtain actual dielectric thickness, copper weights, and material Dk values from the PCB shop that will build the boards
- • Do not use generic stack-ups from field solver libraries
- • Real fabrication parameters differ from idealized models
- Calculate trace width: Use field solver (Polar Si9000, ADS LineCalc, or fabricator tool) with actual stack-up parameters
- Verify with fabricator: Send calculated trace widths back to the shop for validation against their process capability
- Specify tolerance in fab notes: Call out impedance targets and tolerance (example: 50 ohms plus or minus 5 percent)
- Request impedance coupon testing: First article boards should include test coupons that match actual trace geometry
If trace width is calculated using generic stack-up data instead of fabricator-verified parameters, measured impedance can differ from target by 5 to 10 ohms.
Differential Impedance Control and Odd-Mode Coupling
Differential pairs require control of both differential impedance (Zdiff) and odd-mode impedance (Zodd).
Microstrip Differential Pair
- • Trace width: 5 mils
- • Spacing: 8 to 10 mils
- • Zdiff: 100 ohms
- • Zodd: 50 ohms
Stripline Differential Pair
- • Trace width: 4 mils
- • Spacing: 6 to 8 mils
- • Zdiff: 100 ohms
- • Zodd: 50 ohms
Odd-Mode and Even-Mode Impedance
Odd-mode (Zodd): Impedance when driven differentially. For 100-ohm differential, Zodd should be 50 ohms.
Even-mode (Zeven): Impedance when both traces carry the same signal. Typically 90 to 110 ohms for most differential designs.
Specifying both Zdiff and Zodd in fabrication notes ensures the shop controls trace spacing as well as width. Spacing tolerance directly affects coupling and therefore odd-mode impedance.
Impedance Coupon Testing and Acceptance Criteria
Impedance coupons are test structures fabricated on the same panel as the production boards. They use the same trace geometry, layer stack-up, and materials.
Typical Acceptance Criteria for Controlled Impedance
For PCIe Gen 4 and Gen 5, USB 3.2, and 100G Ethernet, plus or minus 5 to 7 percent tolerance is recommended. Default shop tolerance of plus or minus 10 percent is often insufficient.
TDR Measurement of Controlled Impedance Traces
TDR (Time-Domain Reflectometry) provides direct impedance measurement across the length of a trace. Unlike coupon testing, TDR can validate impedance on actual production boards.
Common TDR Impedance Signatures
If TDR shows impedance consistently outside specification, the issue is systematic (process or stack-up error). If variation is random, investigate glass weave alignment or resin distribution.
Common Impedance Failures and Fixes
Impedance too high
Possible causes:
- • Trace width narrower than designed
- • Dielectric thickness greater than expected
- • Over-etch during fabrication
Fix: Increase trace width or reduce dielectric thickness on next revision
Impedance too low
Possible causes:
- • Trace width wider than designed
- • Dielectric thickness less than expected
- • Copper plating thicker than modeled
Fix: Decrease trace width or increase dielectric thickness on next revision
Impedance variation across panel
Possible causes:
- • Non-uniform lamination pressure
- • Resin flow variation
- • Etch inconsistency edge-to-center
Fix: Work with fabricator to improve process uniformity
Differential mode conversion high
Possible causes:
- • Trace spacing inconsistent
- • One trace wider than the other
- • Via placement asymmetry
Fix: Tighten spacing tolerance specification and verify cross-section
Validate Stack-Up Before Layout
Controlled impedance PCB fabrication requires coordination between design and manufacturing from the beginning.
Request fabricator-verified stack-up parameters before calculating trace widths. This single step prevents the majority of impedance failures.