This article is part of our High-Frequency PCB Fabrication Guide.
Simulation tells you what the board should do.
Measurement tells you what it actually does.
Above 10 GHz, the gap between those two answers is rarely zero. Copper roughness, material Df variation, unmodeled via stubs, and solder mask loading all shift measured performance away from simulation. Only physical measurement reveals the true behavior.
S-parameter measurement and time-domain reflectometry are the two primary tools for validating high-frequency PCB performance. They answer different questions. Used together on first articles, they detect problems before production release or customer qualification testing.
This guide explains when to use each method, how to set them up correctly, how to interpret results, and how to resolve discrepancies between measurement and simulation.
S-Parameters: What They Measure and Why They Matter
S-parameters describe how RF energy propagates through a network as a function of frequency. For a two-port network such as a PCB transmission line:
S11 (return loss) measures reflected energy at Port 1. Values should be better than -15 dB across the band. Tight designs target better than -20 dB.
S21 (insertion loss) measures transmitted energy from Port 1 to Port 2. S21 should match simulation within 0.5 to 1 dB. Larger deviations indicate missing physical effects in the model.
S12 equals S21 for passive reciprocal networks.
S31 and S41 measure crosstalk. Isolation should be better than -30 dB. Values above -25 dB indicate coupling concerns.
For differential pairs:
- Sdd21 measures differential insertion loss
- Scc21 measures common-mode insertion loss
- Sdc21 and Scd21 measure mode conversion
Mode conversion should remain below -30 dB. Higher values indicate asymmetry in routing, via placement, or coupling.
Target Values by Interface
| Interface | S11 Target | S21 Limit | Mode Conversion | Standard |
|---|---|---|---|---|
| PCIe Gen 3 | <-10 dB @ 1-8 GHz | Per channel budget | <-30 dB | PCI-SIG |
| PCIe Gen 4 | <-10 dB @ 1-16 GHz | Per channel budget | <-30 dB | PCI-SIG |
| PCIe Gen 5 | <-10 dB @ 1-32 GHz | Per channel budget | <-30 dB | PCI-SIG |
| 100G Ethernet | <-10 dB @ 12.5 GHz | <6 dB (10 inch) | <-30 dB | IEEE 802.3 |
| 50-ohm RF trace | <-15 dB across band | Per design budget | N/A | Design spec |
Minimum thresholds are not design targets. A board passing at -10.1 dB return loss has no production margin.
TDR: What It Measures and When to Use It
Time-domain reflectometry launches a fast edge into the transmission line and measures reflections versus time. Time maps directly to physical distance, allowing localization of impedance discontinuities.
S-parameters answer: How does the board perform across frequency?
TDR answers: Where is the impedance problem physically located?
TDR is ideal for prototype debug. If TDR shows a 10-ohm dip 3 inches into a 6-inch trace, inspection focuses at that location.
Common TDR Signatures
| Signature | Probable Cause |
|---|---|
| Gradual impedance rise | Dielectric thickness variation |
| Sharp localized dip | Via stub or reference plane gap |
| Uniform low impedance | Dielectric thicker than nominal |
| Uniform high impedance | Dielectric thinner than nominal |
| Periodic ripple | Glass weave effect |
TDR cannot measure frequency-dependent loss. A trace may show flat impedance on TDR but poor insertion loss at high frequency.
VNA Calibration: Why It Matters
A vector network analyzer measures cables, connectors, and fixtures along with the device under test. Calibration shifts the measurement reference plane to the DUT input.
SOLT Calibration
- Short, Open, Load, Thru standards
- Effective to 20-30 GHz
- Common for coaxial testing
TRL Calibration
- Thru, Reflect, Line method
- Preferred above 20 GHz
- Best for on-board launch structures
Common errors include calibrating only to cable end, using worn connectors, bending cables after calibration, or ignoring temperature drift.
De-Embedding: Removing Fixture Effects
Test fixtures add parasitics. De-embedding mathematically removes fixture contribution to isolate DUT performance.
A typical procedure includes fabricating dedicated thru and open standards, measuring them, and applying half-fixture de-embedding to DUT data.
Above 20 GHz, de-embedding is mandatory for accurate characterization.
When Measurements Disagree with Simulation
A delta of 0.5 to 1 dB in S21 is common for first articles. Copper roughness and material Df variation are typical causes.
Delta of 1 to 2 dB requires investigation. Check roughness modeling, material lot variation, solder mask loading, and residual via stubs.
Delta greater than 2 dB indicates a systematic issue. Cross-section, verify stack-up, and validate material properties before production release.
If measured data conflicts with simulation by more than 1 dB, investigate before proceeding.
First Article Validation Procedure
- Measure impedance coupons with TDR
- Measure representative critical nets
- Perform S11 and S21 validation across operating band
- Validate differential Sdd21 and Sdc21
- Cross-section critical vias
- Compare measured results to simulation within 1 dB
Do not release to assembly if S21 deviation exceeds 2 dB or S11 fails specification.
Production Monitoring
- Track impedance coupon TDR for every panel
- Flag average impedance shifts greater than 2 ohms
- Periodically re-measure S-parameters on production lots
- Treat new material lots as new first articles
Material Df variation between lots can shift S21 by 0.3 to 0.5 dB on a 6-inch trace at 10 GHz.
Next Step
For designs above 10 GHz, S-parameter and TDR validation should occur before production release.
Request first-article measurement support
Request a fabrication and assembly quote
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